Field Programmable Gate Array (FPGA) based computing board, working as a co-processor together with the host, can be used to speedup computational intensive and data intensive algorithms. Designers decide whether the board can meet the application requirements by estimating the maximal speedup according to the board constraints. A fast and accurate estimation method is presented here for Sliding Window Operation
(SWO) based applications, which is widely used in image processing. By
defining three upper bounds according to area constraints, memory bandwidth and on-chip memory size constraints, the maximal speedup is estimated and a corresponding hardware block structure is also determined at the same time.
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