PRATE will open up new and exciting areas in networking research. It will provide several hardware platforms with P4 to FPGA implementations. This fills a gap in current infrastructure as P4 to FPGA tool flows are not currently available on public clouds. PRATE will enable research across a range of cloud computing systems and applications. These network attached accelerators will enable innovative research into network security, in-network telemetry and in-network processing.
P4-Tutorial-FPGA is a set of examples implemented on FPGA on OCT. It will demonstrate a framework of combining Xilinx OpenNIC with P4. Researchers can develop and deploy their own P4 codes using the same same framework as we demonstrated.
GithubThis is funded by NSF 2130891:EAGER: Collaborative Research: CNS: PRATE: P4 Research enabled by Accelerators in national TestbEds .