Journal Articles
- Validity and Reliability of Kinect Skeleton for Measuring Shoulder Joint Angles,
Meghan Huber, Amee L. Seitz,
Miriam Leeser, and
Dagmar Sternad.
Physiotherapy.
Accepted for publication, February, 2015.
- Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry,
N. Moore,
Miriam Leeser, and
Laurie Smith King.
IEEE Trans. on Parallel and Distributed Systems.
Volume 26 Number 4, pp. 1049-1058, April 2015.
DOI: 10.1109/TPDS.2014.2317721.
- Fast reconstruction of 3D volumes from 2D CT projection data with GPUs,
Miriam Leeser,
Saoni Mukherjee and James Brock.
Biomed Central Research Notes 2014, 7:582.
DOI:10.1186/1756-0500-7-582.
- Minimum Energy Analysis and Experimental Verification of a
Latch-Based Subthreshold FPGA,
Peter Grossmann,
Miriam Leeser,
Marvin Onabajo.
IEEE Trans. on Circuits and Systems II: Express Briefs.
(Special issue on Ultra-Low Voltage VLSI Circuits and Systems for Green Computing).
Volume 59 Number 12. pp. 942-946, December 2012.
- VForce: An Environment for Portable Applications on High
Performance Systems with Accelerators,
Nicholas Moore,
Miriam Leeser,
Laurie Smith King,
Journal of Parallel and Distributed Computing
(Special issue on Accelerators for High Performance Computing).
Volume 72 Issue 9. pp. 1144-1156,
September 2012.
- The Challenges of Writing Portable, Correct and High
Performance Libraries for GPUs,
Miriam Leeser,
Devon Yablonski,
Dana Brooks,
Laurie Smith King,
ACM SIGARCH Computer Architecture News. Volume 39 Issue 4. pp. 2-7,
September 2011.
-
VFloat: Variable Precision Fixed and Floating-Point Arithmetic and
its Use in a K-means Clustering Application,
Xiaojun Wang and
Miriam Leeser,
ACM Transactions on Reconfigurable Technology and
Systems. Volume 3 Number 3, September 2010.
-
A Truly Two Dimensional Systolic Array FPGA Implementation of QR Decomposition,
Xiaojun Wang and
Miriam Leeser,
ACM Transactions on Embedded Computer Systems. Volume 9
Number 1, October 2009.
-
Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing,
Ben Cordes and
Miriam Leeser,
EURASIP Journal on Embedded Systems Special Issue on
FPGA Supercomputing Platforms, Architectures and Techniques for Accelerating
Computationally Complex Algorithms. Volume 2009.
- Efficient Communication Between the Embedded Processor and the
Reconfigurable Logic on an FPGA, Josh Noseworthy and
Miriam Leeser,
IEEE Transactions on VLSI Systems. Volume 16 Number 8. pp. 1083-1090,
August 2008.
- Dynamo: A Runtime Partitioning System for FPGA-based HW/SW Image
Processing Systems, Heather Quinn,
Miriam Leeser and
Laurie Smith King. Journal of
Real-Time Image Processing. Volume 2, Number 4, pp. 179-190, December
2007.
- Vforce: An Extensible Framework for Reconfigurable Supercomputing,
Nicholas Moore, Albert Conti
Miriam Leeser and
Laurie Smith King.
IEEE Computer Magazine. Volume 40, Number 3, pp. 39-49, March 2007.
- Field-Programmable Gate Arrays in Embedded Systems,
Miriam Leeser,
Scott Hauck, and Russell Tessier.
EURASIP
Journal on Embedded Systems. Volume 2006.
- Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA
Implementation, Haiqian Yu,
Miriam Leeser and
Gilead Tadmor, and Stefan Siegel Journal of Aerospace Computing,
Information, and Communication. Volume 3, No. 2, pp. 52-62, February 2006.
- Enabling MPEG-2 Video Playback in Embedded Systems Through Improved
Data Cache Efficiency, Peter Soderquist,
Miriam Leeser
and Juan Carlos Rojas. IEEE Transactions on Multimedia. Volume 8, No. 1, pp.
81-89, February 2006.
-
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical
Imaging, Miriam Leeser,
Srdjan Coric,Eric Miller,
Haiqian Yu and Marc Trepanier. Journal of VLSI Signal Processing. Vol. 39,
No. 3, pp. 295-311, 2005.
- Accurate Power Estimation for Sequential CMOS Circuits using
Graph-based Methods,
Miriam Leeser
and Valerie Ohm. VLSI Design, An International Journal of Custom-Chip
Design, Simulation and Testing. Special Issue on Low-Power Design.
Vol. 12, No. 2, pp. 187-203, 2001.
-
Design and Analysis of a Dynamically Reconfigurable Three-Dimensional
FPGA, Silviu Chiricescu,
Miriam Leeser and
M. Michael Vai. IEEE Transactions on VLSI Systems, Special Issue on
Reconfigurable and Adaptive VLSI Systems. Vol. 9, No. 1, pp. 186-196,
February 2001.
-
A Data-Centric Approach to High-Level Synthesis, Shantanu Tarafdar and
Miriam Leeser.
IEEE Transactions on Computer-Aided Design, Vol. 19, No. 11, pp.
1251-1267, November 2000.
- HML: A Novel Hardware Description Language, and its Translation
to VHDL, Yanbing Li and
Miriam Leeser.
IEEE Transactions on VLSI Systems, Vol. 8, No. 1, pp. 1-8, January 2000.
-
Rothko: A Three Dimensional {FPGA},
Miriam Leeser,
Waleed M. Meleis ,
M. Vai, S. Chiricescu, W. Xu and
Paul Zavracky.
IEEE Design and Test of Computers, Vol. 15, No. 1, pp. 16-23,
January-March, 1998.
- Division and Square Root: Choosing the Right
Implementation, Peter Soderquist and
Miriam Leeser.
IEEE Micro, Vol. 17, No. 4, pp. 56-66, July/August 1997.
-
Area and Performance Tradeoffs in Floating-Point Division and Square Root
Implementations, Peter Soderquist and
Miriam Leeser.
ACM Computing Surveys, Vol. 28, No. 3, pp. 518-564, September 1996.
- Verifying a Logic-Synthesis Algorithm and Implementation: A
Case Study in Software Verification,
Mark Aagaard and
Miriam Leeser.
IEEE Transactions on Software Engineering, Vol. 21, No. 10, pp. 822-833,
October 1995.
- An Automaton Model for Scheduling Constraints, Andres Takach, Wayne
Wolf, and
Miriam Leeser.
IEEE Transactions on Computers, Vol. 44, No. 1, pp. 1-12, January 1995.
- A Methodology for Efficient Hardware Verification,
Mark Aagaard and
Miriam Leeser.
Journal of Formal Methods in System Design, Vol. 5, Nos. 1/2,
pp. 95-117, July 1994.
-
PBS: Proven Boolean Simplification,
Mark Aagaard and
Miriam Leeser.
IEEE Transactions on Computer-Aided Design, Vol. 13, No. 4, pp. 459-470,
April 1994.
- High Level Synthesis and Generating FPGAs with the BEDROC System,
Miriam Leeser,
Richard Chapman, Mark Aagaard,
Mark Linderman, and Stephan Meier.
Journal of VLSI Signal Processing, Vol. 6, No. 2, pp. 191-214, 1993.
- Using Nuprl for the Verification and Synthesis of Hardware,
Miriam Leeser.
Philosophical
Transactions of the Royal Society, A. Vol. 339, pp. 49-68, 1992.
-
Formally Verified Synthesis of Combinational CMOS Circuits,
David A. Basin, Geoffrey M. Brown, and
Miriam Leeser.
Integration, the VLSI Journal, Vol. 11, Issue 3, pp. 235-250, June 1991.
-
Reasoning about the Function and Timing of Integrated Circuits with
Interval Temporal Logic,
Miriam Leeser.
IEEE Transactions on Computer-Aided Design, Vol. 8, No. 12, pp. 1233-1246,
December 1989.
-
Automatic Determination of Signal Flow through MOS Transistor Networks,
W. F. Clocksin and
Miriam Leeser.
Integration, the VLSI Journal, Vol. 4, Issue 1, pp. 53-63, March 1986.
Conference Papers
- Accelerating K-Means Clustering with Parallel Implementations and GPU computing,
Janki Bhimani, Miriam Leeser, Ningfang Mi.
Nineteenth IEEE High-Performance Extreme Computing
Conference (HPEC). September 2015.
- GPU Implementation of Reverse Coordinate Conversion for Proteins,
Mahsa Bayati, Jaydeep P. Bardhan, Miriam Leeser.
Nineteenth IEEE High-Performance Extreme Computing
Conference (HPEC). September 2015.
- Leakage Evaluation on Power Balance Countermeasure Against Side-Channel Attack on FPGA,
Xin Fang, Pei Luo, Yunsi Fei, and Miriam Leeser.
Nineteenth IEEE High-Performance Extreme Computing
Conference (HPEC). September 2015.
- Behavioral Non-portability in Scientic Numeric Computing,
Y. Gu, T. Wahl, M. Bayati and M. Leeser.
Euro-Par International Conference on Parallel and Distributed Computing,
pp. 558-569, August 2015.
- Side-channel Analysis of MAC-Keccak Hardware Implementations,
P. Luo, Y.Fei, X. Fang, A. Ding, D. Kaeli, and M. Leeser.
Hardware and Architectural Support for Security and Privacy, June 2015.
- Implementing a MATLAB-based Self-Configurable Software-Defined Radio Transceiver,
Benjamin Drozdenko, Ramanathan Subramanian, Kaushik Chowdhury, and Miriam Leeser.
10th International Conference on Cognitive Radio Oriented Wireless Networks (CROWN-COM).
April, 2105.
- Power Analysis Attack on Hardware Implementation of MAC-Keccak on FPGAs,
Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser and David R. Kaeli.
International Conference on ReConFigurable Computing and FPGAs.
Cancun, Mexico. December 2014.
- Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework,
J. Pendlum, M. Leeser and K. Chowdhury.
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM),
May 2014.
- Make it real: Eective floating-point reasoning via exact arithmetic,
Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran and Thomas Wahl.
Design, Automation & Test in Europe Conference (DATE), March 2014.
-
Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs),
N. Moore, M. Leeser and L. Smith King.
27th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2013),
pp. 1037-1048,
May 2013.
- Characterization of a Single-Supply Subthreshold FPGA,
Peter Grossmann, Miriam Leeser, and Marvin Onabajo.
In IEEE Subthreshold Microelectronics Conference.
October 2012.
-
CUDA and OpenCL Implementations of 3D CT Reconstruction for Biomedical Imaging,
Saoni Mukherjee, Nicholas Moore, James Brock and Miriam Leeser.
In Sixteenth IEEE High-Performance Extreme Computing Conference (HPEC2012).
September 2012.
- CRUSH: Cognitive Radio Universal Software Hardware,
George Eichinger, Kaushik Chowdhury and
Miriam Leeser.
22nd International Conference on Field Programmable Logic and Applications (FPL),
August 2012.
- OpenCL Floating Point Software on Heterogeneous Architectures --Portable or Not?,
Miriam Leeser, Jaideep Ramachandran, Thomas Wahl, and Devon Yablonski.
In Fifth International Workshop on Numerical Software Verification (NSV).
July 2012.
- Heterogeneous Tasks and Conduits Framework for Rapid Application Portability and Deployment.
J. Brock and
Miriam Leeser.
Innovative Parallel Computing. Foundations & Applications of GPU, Manycore,
and Heterogeneous Systems,
May 2012.
- Incremental Clustering Applied to Radar Deinterleaving: A Parameterized FPGA Implementation.
Scott Bailie and
Miriam Leeser.
20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA),
February 2012.
- Circuit-Level Considerations for an Ultra-Low Voltage FPGA
with Unidirectional, Single-Driver Routing Fabric,
Peter Grossmann and
Miriam Leeser,
IEEE SubVt Microelectronics Conference, MIT Lincoln Laboratory,
September 2011. talk (pdf)
- Adaptable Two-Dimension Sliding Windows on NVIDIA GPUs with Runtime Compilation,
N. Moore, M. Leeser and L. Smith King.
paper available in pdf.
slides available in pdf.
SAAHPC: Symposium on Application Accelerators in High Performance Computing,
July 2011. Winner, Best Paper Award!
- An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs.
J. Kathiara and
Miriam Leeser.
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) ,
May 2011.
- Accelerating Algorithms on GPUs in SCIRun: the Conjugate Gradient Case Study,
D. Yablonski, M. Leeser and D. Brooks.
In Symposium on Application Accelerators in High Performance Computing (SAAHPC),
July 2010.
- Efficient Template Matching with Variable Size Templates in CUDA,
N. Moore, M. Leeser and L. Smith King.
IEEE Symposium on Application Specific Processors (SASP),
June 2010.
- Using Variable Precision Floating Point with Embedded Hard and Soft Core Processors,
J. Kathiara, M. Leeser and P. Palana.
In Field Programmable Custom Computing Machines (FCCM 2010),
May 2010.
-
The Effect of Parameterization on a Reconfigurable Implementation of PIV.
A. Bennis,
Miriam Leeser, and
G. Tadmor.
Engineering of Reconfigurable Systems and Algorithms (ERSA),
July 2009.
-
Implementing a Highly Parameterized Digital PIV System On Reconfigurable Hardware.
A. Bennis,
Miriam Leeser, and
G. Tadmor.
IEEE International Conference Application-specific Systems,
Architectures and Processors,
July 2009.
- An FPGA Implementation of Explicit-State Model Checking,
M.E. Fuess Miriam Leeser,
and T. Leonard.
IEEE Symposium on Field-Programmable Custom Computing
Machines (FCCM2008), pp. 119-126. April 2008.
- K-means Clustering for Multispectral Images Using Floating-Point
Divide, Xiaojun Wang,
Miriam Leeser,
and IEEE Symposium on Field-Programmable Custom Computing Machines
(FCCM2007), pp. 151-162. Napa, CA. April 23-25, 2007.
- Writing Portable Applications that Dynamically Bind at Run Time to
Reconfigurable Hardware, Nicholas Moore, Albert Conti,
Miriam Leeser, and
Laurie Smith King.
IEEE Symposium on Field-Programmable Custom Computing Machines
(FCCM2007), pp. 229-238. Napa, CA. April 23-25, 2007.
- Efficient use of Communications Between an FPGA's Embedded Processor
and its Reconfigurable Logic, Joshua Noseworthy and
Miriam Leeser.
Engineering of Reconfigurable Systems and Algorithms (ERSA2006),
pp. 191-197. June 2006.
- Advanced Components in the Variable Precision Floating-Point Library,
Xiaojun Wang, Sherman Braganza, and
Miriam Leeser.
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2006),
pp. 249-258. April 2006.
- Automatic Sliding Window Operation Optimization for FPGA-Based
Computing Boards, Haiqian Yu and
Miriam Leeser.
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2006),
pp. 147-155. April 2006.
- Optimizing Data Intensive Window-Based Image Processing on
Reconfigurable Hardware Boards, Haiqian Yu and
Miriam Leeser.
IEEE 2005 Workshop on Signal Processing Systems (SIPS'05). November 2005.
-
Enabling a Real-Time Solution for Neuron Detection with Reconfigurable
Hardware, Ben Cordes,
Jennifer Dy,
Miriam Leeser and
James Goebel. The 16th IEEE International Workshop on Rapid System
Prototyping, June 2005.
- Dynamo, a Run-Time Partitioning System,
Laurie Smith King,
Miriam Leeser,
Heather Quinn.
Engineering of Reconfigurable Systems and Algorithms (ERSA2004),
pp. 145-151. June 2004.
-
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-time
Applications,
Miriam Leeser,
Shawn Miller and Haiqian Yu. IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM2004), pp. 147-155. April 2004.
-
An FPGA Implementation of the Two-Dimensional Finite-Difference
Time-Domain (FDTD) Algorithm , Wang Chen, Panos Kosmas,
Miriam Leeser and
Carey Rappaport. Twelfth {ACM} International Symposium on
Field-Programmable Gate Arrays (FPGA2004), pp. 213-222. February 2004.
- Precision Modeling of Floating-Point Applications for Variable
Bitwidth Computing, Zhihong Zhao and
Miriam Leeser.
International
Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA2003), pp. 208-214. June 2003.
-
Runtime Assignment of Reconfigurable Hardware Components for Image
Processing Pipelines, Heather Quinn,
Laurie Smith King,
Miriam Leeser,
Waleed Meleis.
IEEE Symposium on Field-Programmable Custom Computing Machines
(FCCM2003), pp. 173-182. April 2003.
- A Library of Parameterized Floating Point Modules and Their Use, Pavle
Belanovic and
Miriam Leeser.
12th International Conference on Field Programmable Logic and
Application (FPL2002), pp. 657-666. September 2002.
-
Parallel-Beam Backprojection: an FPGA Implementation Optimized for
Medical Imaging, Srdjan Coric,
Miriam Leeser,
Eric Miller,
Marc Trepanier. Tenth {ACM} International Symposium on Field-Programmable
Gate Arrays (FPGA2002), pp. 217--226. February 2002.
-
Runtime Execution of Reconfigurable Hardware in a Java Environment,
Laurie Smith King, Heather Quinn,
Miriam Leeser,
Dimitri Galatopoullos,
Elias Manolakos.
International Conference on Computer Design (ICCD 2001), pp. 380--385.
September 2001.
-
Algorithmic Transformations in the Implementation of K-means Clustering
on Reconfigurable Hardware, Mike Estlick,
Miriam Leeser,
James Theiler, John J. Szymanski. Ninth {ACM} International Symposium on
Field-Programmable Gate Arrays (FPGA2001), pp. 103--110. February 2001.
-
Implementing a RAKE Receiver for Wireless Communications on an FPGA-based
Computer System, Ali M. Shankiti and
Miriam Leeser.
Eighth ACM International Symposium on Field-Programmable Gate Arrays
(FPGA2000). pp. 145--151, February 2000.
-
Integrating Floorplanning In Data-Transfer Based High-Level Synthesis,
Shantanu Tarafdar,
Miriam Leeser and
Zixin Yin. IEEE/ACM International Conference on CAD-98, pp. 412--417,
November 1998.
-
The DT-Model: High-Level Synthesis Using Data Transfers, Shantanu
Tarafdar and
Miriam Leeser.
35th ACM/IEEE Design Automation Conference, pp. 114--117, June 1998.
-
Truly Rapid Prototyping Requires High Level Synthesis, Goran Doncev,
Miriam Leeser and
Shantanu Tarafdar. 9th IEEE International Workshop on Rapid System
Prototyping, pp. 101--106, June 1998.
-
Optimizing the Data Cache Performance of a Software MPEG-2 Video
Decoder, Peter Soderquist and
Miriam Leeser.
ACM Multimedia'97, pp. 291--301, November 1997.
-
Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder,
Peter Soderquist and
Miriam Leeser.
International Conference on Computer Design (ICCD'97), pp. 417--422,
October 1997.
- Architectural Design of a Three Dimensional FPGA, Waleed Meleis,
Miriam Leeser,
Paul Zavracky and Mankuan Vai. 17th Conference on Advanced Research in
VLSI (ARVLSI'97), pp. 256--268, September 1997.
-
Verification of a Subtractive Radix-2 Square Root Algorithm and
Implementation,
Miriam Leeser and
John O'Leary. 1995 IEEE International Conference on Computer Design,
pp. 526--531, October 1995.
- {HML}: An Innovative Hardware Description Language and Its Translation
to {VHDL}, Yanbing Li and
Miriam Leeser.
Proceedings, IFIP International Conference on Computer Hardware
Description Languages and their Applications, pp. 691--696, August 1995.
-
An Area/Performance Comparison of Subtractive and Multiplicative
Divide/Square Root Implementations, Peter Soderquist and
Miriam Leeser.
12th IEEE Symposium on Computer Arithmetic, pp. 132--139, July 1995.
-
Simulation of Digital Circuits in the Presence of Uncertainty,
Mark Linderman and
Miriam Leeser.
1994 IEEE International Conference on Computer-Aided Design, pp. 248--251,
November 1994.
- Non-Restoring Integer Square Root: A Case Study in Design by
Principled Optimization, John O'Leary,
Miriam Leeser,
Jason Hickey and Mark Aagaard.
1994 International Conference on Theorem Provers in Circuit Design,
October 1994. Published in Vol. 901 of Lecture Notes in Computer
Science, (T. Kropf and R. Kumar, eds.), pp. 52--71, Springer Verlag, 1995.
- Reasoning about Pipelines with Structural Hazards,
Mark Aagaard and
Miriam Leeser.
1994 International Conference on Theorem Provers in Circuit Design,
October 1994. Published in Vol. 901 of Lecture Notes in Computer
Science, (T. Kropf and R. Kumar, eds.), pp. 13--32, Springer Verlag, 1995.
-
A Framework for Specifying and Designing Pipelines,
Mark Aagaard and
Miriam Leeser.
Proceedings, 1993 IEEE International Conference on Computer Design, IEEE
Computer Society Press, pp. 548--551, October 1993.
- Implementing Floating-Point Square Root Computation with Newton's
Method, Peter Soderquist and
Miriam Leeser.
International Workshop on Hardware-Software Co-design. Cambridge, MA,
October 1993.
- HML: A Hardware Description Language Based on SML, John O'Leary,
Mark Linderman,
Miriam Leeser and
Mark Aagaard.
D. Agnew, L. Claesen and R. Camposano, eds, IFIP Conference on Hardware
Description Languages and their Applications, pp. 313--320, April 1993.
- Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software
Verification,
Mark Aagaard and
Miriam Leeser.
Fourth Workshop on Computer Aided Verification. Montreal, Canada, June 1992.
- Verified High-Level Synthesis in BEDROC, Richard Chapman, Geoffrey
Brown and
Miriam Leeser.
EDAC 92, The European Conference on Design Automation, pp. 59--63, March 1992.
-
A Formally Verified System for Logic Synthesis,
Mark Aagaard and
Miriam Leeser.
Proceedings, 1991 IEEE International Conference on Computer Design, IEEE
Computer Society Press, pp. 346--350, October 1991.
- The BEDROC High Level Synthesis System,
Miriam Leeser,
Mark Aagaard,
Mark Linderman, Richard Chapman, Richard Johnson and Stephan Meier.
Proceedings, Fourth Annual IEEE International ASIC Conference and
Exhibit, pp. 2-5.1 -- 2-5.5, IEEE Computer Society Press, September 1991.
- Hardware Scheduling with Real-Time A* Search,
Miriam Leeser
and Stephan Meier. Fifth International Workshop on High-Level Synthesis,
Germany, March 1991.
- Preserving Design Behavior without Register-Transfer Equivalence,
Miriam Leeser and
Wayne Wolf. Fifth International Workshop on High-Level Synthesis, Germany,
March 1991.
- Behavior FSMs for High-Level Verification and Synthesis,
Miriam Leeser and
Wayne Wolf. ACM Workshop on Formal Methods in VLSI Design, Miami FL,
January 1991.
- Synthesizing Correct Sequential Circuits, Geoffrey Brown and
Miriam Leeser.
J. A. Darringer and F. J. Rammig, eds, International Conference on
Computer Hardware Description Languages, North-Holland, pp. 169--182,
January 1990.
- Verifying High-Level Hardware Synthesis Tools,
Miriam Leeser
and Geoffrey Brown. Fourth International Workshop on High-Level Synthesis,
October 1989.
PhD Dissertations
- Peter Grossmann,
Design and Analysis of Minimum Energy FPGAs
[PDF]
[ABSTRACT] ,
Northeastern University, 2013.
- James Brock,
An Environment to Support GPU and Multicore Programming for Rapid,
High Performance, Application Deployment
[PDF]
[ABSTRACT] ,
Northeastern University, 2012.
- Nicholas Moore,
Kernel Specialization for Improved Adaptability and Performance on
Graphics Processing Units (GPUs)
[PDF]
[ABSTRACT] ,
Northeastern University, 2012.
- Abderrahmane Bennis,
Implementing a Highly Parameterized Digital PIV System On
Reconfigurable Hardware
[PDF]
[ABSTRACT] ,
Northeastern University, August 2010.
- Xiaojun Wang, Variable Precision Floating-Point Divide and
Square Root for Efficient FPGA Implementation of Image and Signal
[PDF]
[ABSTRACT] ,
Northeastern University, January 2008.
- Wang Chen, Acceleration of the 3D FDTD Algorithm in Fixed-point
Arithmetic using Reconfigurable Hardware
[PDF]
[ABSTRACT] ,
Northeastern University, August 2007.
- Haiqian Yu, Optimizing Data Intensive Windo w-based Image
Processing on Reconfigurable Hardware Boards
[PDF]
[ABSTRACT] ,
Northeastern University, May 2007.
- Heather Quinn, Runtime Tools for Hardware/Software Systems with
Reconfigurable Hardware
[PDF]
[ABSTRACT] ,
Northeastern University, August 2004.
- Juan Carlos Rojas, Multimedia Macros for Portable Optimized
Programs
[PDF]
[ABSTRACT] ,
Northeastern University, August 2003.
- Silviu Chiricescu, Parametric Analysis of a Dynamically
Reconfigurable Three-Dimensional FPGA
[] ,
Northeastern University, June 2000.
- Valerie Ohm, Power Estimation for Combinational and Sequential
CMOS Circuits using Graph-Based Methods
[] ,
Cornell University, May 1999.
- Peter Soderquist, Cache-Sensitive Architectural Optimizations
for MPEG-2 Video Decoding
[] ,
Cornell University, May 1998.
- Shantanu Tarafdar, A Data-Transfer Model for High Level Synthesis
and Its Application in Storage and Interconnect Optimization
[] ,
Cornell University, May 1998.
- Mark Linderman, Simulation of Digital Circuits in the Presence
of Uncertainty
[] ,
Cornell University, January 1995.
- Mark Aagaard, A Framework for the Specification, Design, and
Verification of Pipelines with Structural Hazards
[] ,
Cornell University, January 1995.
Master's Theses
- Mahsa Bayati,
Parallel Methods for Protein Coordinate Conversion
[PDF]
[ABSTRACT] ,
Northeastern University, April 2015.
- Jonathon Pendlum,
CRASH: Cognitive Radio Accelerated with Software and Hardware
[PDF]
[ABSTRACT] ,
Northeastern University, April 2014.
- Xin Fang,
Variable Precision Floating Point Reciprocal, Division and Square Root for Major FPGA Vendors
[PDF]
[ABSTRACT] ,
Northeastern University, July 2013.
- David Kusinsky,
FPGA-based Hyperspectral Covariance Coprocessor for Size, Weight, and Power Constrained Platforms
[PDF]
[ABSTRACT] ,
Northeastern University, 2013.
- George Eichinger,
CRUSH: Cognitive Radio Universal Software Hardware
[PDF]
[slides, PDF]
[ABSTRACT] ,
Northeastern University, April 2012.
- Mary Ellen Tie,
Accelerating Explicit State Model Checking on an FPGA: PHAST
[PDF]
[ABSTRACT] ,
Northeastern University, defended February 2012.
- Devon Yablonski,
Numerical Accuracy Differences in CPU and GPGPU Codes
[PDF]
[ABSTRACT] ,
Northeastern University, defended, April 2011.
- Jainik Kathiara,
The Unified Floating Point Vector Co-processor (FPVC)
[PDF]
[ABSTRACT]
, Northeastern University, January 2011.
- Scott Bailie,
An FPGA Implementation of Incremental Clustering for Radar Pulse Deinterleaving
[PDF]
[ABSTRACT]
, Northeastern University, April 2010.
- Sherman Braganza, Phase Unwrapping on FPGAs and GPUs
[PDF]
[ABSTRACT]
, Northeastern University, August 2008.
- Ben Cordes, Parallel Backprojection: A Case Study in High
Performance Reconfigurable Computing
[PDF]
[ABSTRACT]
, Northeastern University, May 2008.
- Nick Moore, Vforce: VSIPL++ for Reconfigurable Computing
Environments
[PDF]
[ABSTRACT]
, Northeastern University, defended December 2007.
- Albert Conti, A Hardware/Software System for Adaptive Beamforming
[PDF]
[ABSTRACT]
, Northeastern University, May 2007.
- Joshua Noseworthy, Enabling Communications Between an FPGA's
Embedded Processor and its Reconfigurable Resources
[PDF]
[ABSTRACT]
, Northeastern University, August 2005.
- Shawn Miller, Enabling a Real-time Solution to Retinal Vascular
Tracing Using FPGAs
[PDF]
[ABSTRACT]
, Northeastern University, April 2004.
- Wang Chen, An FPGA Implementation of the 2D FDTD Algorithm
[PDF]
[ABSTRACT]
, Northeastern University, August 2003.
- Haiqian Yu, Memory Architecture of Data Intensive Image
Processing Algorithms in Reconfigurable Hardware
[PDF]
[ABSTRACT]
, Northeastern University, August 2003.
- Michael Estlick, An FPGA Implementation of the K-Means
Algorithm for Image Processing
[ABSTRACT]
, Northeastern University, September 2002.
- Srdjan Coric, Parallel-Beam Backprojection: an FPGA
Implementation Optimized for Medical Imaging
[PDF]
[ABSTRACT]
, Northeastern University, September 2002.>
- Pavle Belanovic, Library of Parameterized Modules for
Floating-Point Arithmetic with an Example Application
[PDF]
[ABSTRACT]
, Northeastern University, June 2002.
- Natalya Kitaryeva, K-Means Clustering for Color Image
Processing on a Reconfigurable Hardware Board
[]
, Northeastern University, June 2001.
- Heather Quinn, Image Processing Designs in JHDL, a Java-based
Hardware Description Language
[]
, Northeastern University, December 2000.
- Zixin Yin, Global and Incremental Floorplanning for
High-Level Synthesis
[]
, Northeastern University, December 1998.
- Ali Shankiti, Implementing a RAKE Receiver on an FPGA-based
Computer System
[]
, Northeastern University, September 1999.
- Goran Doncev, Mapping DSP Systems onto FPGAs Using Behavioral Synthesis: A Case Study
[]
, Northeastern University, June 1998.
- Yanbing Li, HML: An Innovative Hardware Description Language
and Its Translation to VHDL
[PDF]
, Cornell University, August 1995.
- Peter Soderquist, Area and Performance Tradeoffs in
Floating-Point Division and Square Root Implementations
[]
, Cornell University, January 1995.
- Mark Aagaard, A Formally Verified System for Logic
Synthesis
[]
, Cornell University, January 1992.
Other Papers, Posters and Publications
- Balance Power Leakage to Fight Against Side-Channel Analysis at Gate Level in FPGAs,
Xin Fang, Pei Luo, Yunsi Fei and Miriam Leeser.
IEEE ASAP conference, July 2015.
- Full Duplex 802.11a-Compliant Transceiver with Split Functionalities,
Rahman Doost, Benjamin Drozdenko, Kaushik Chowdhury, and Miriam Leeser.
New England Workshop on Software Defined Radio (NEWSDR), May 2015.
- Bi-Directional Transceiver Implementation with Optimal Parameter Selection,
Benjamin Drozdenko, Ramanathan Subramanian, Kaushik Chowdhury, and Miriam Leeser.
New England Workshop on Software Defined Radio (NEWSDR), May 2015.
- Predicting the Performance of Machine Learning Algorithms running on Heterogeneous Computing Platforms,
Janki Bhimani, Miriam Leeser and Ningfang Mi.
Women in Machine Learning Workshop. December 2014.
- Accuracy and Precision of a Low-Cost Virtual Rehabilitation System Utilizing the Microsoft
Kinect to Measure Shoulder Motion.
A. L. Seitz, M. Huber, M. Leeser, and D. Sternad.
American Society of Shoulder and Elbow Therapists Annual Meeting.
Pinehurst, North Carolina, October, 2014.
-
Accelerating Protein Coordinate Conversion using GPUs,
Mahsa Bayati, Jaydeep Bardhan, D. M. King and Miriam Leeser.
Eighteenth IEEE High-Performance Extreme Computing
Conference (HPEC). September 2014.
- CRASH: Cognitive Radio Accelerated with Software and Hardware,
Jonathon Pendlum, Miriam Leeser, and Frank Bruno.
New England Workshop on Software Defined Radio, May 2014.
- PHY and Link Layer SDR Implementation Using MATLAB,"
Benjamin Drozdenko, Jingzhi Yu, Kaushik Chowdhury, and Miriam Leeser.
New England Workshop on Software Defined Radio, May 2014.
- Validity and Reliability of Kinect for Measuring Shoulder Joint Angles,
M.E. Huber, AL Seitz, M. Leeser and D. Sternad.
IEEE Proceedings of the 40th Northeast Bioengineering Conference. April 2014.
- FPGA-based Hyperspectral Covariance Coprocessor for Size, Weight, and Power,
David Kusinsky and Miriam Leeser.
Seventeenth IEEE High-Performance Extreme Computing Conference (HPEC). September 2013.
- Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs,
Xin Fang and Miriam Leeser.
Seventeenth IEEE High-Performance Extreme Computing Conference (HPEC). September 2013. (Runner up, Best Poster Award.)
- Development of a low-cost, adaptive, clinician-friendly virtual rehabilitation system,
M. E. Huber and M. Leeser and D. Sternad.
International Conference on Virtual Rehabilitation.
August, 2013. (Winner Best Student Poster Award.)
- Characterization of a Single-Supply Subthreshold FPGA,
Peter Grossmann, Miriam Leeser, and Marvin Onabajo.
IEEE Subthreshold Microelectronics Conference. October 2012.
- Cognitive Radio Universal Software Hardware," G. Eichinger, K. R. Chowdhury and M. Leeser.
Proc. of IEEE DySPAN, demonstration session. October, 2012.
- CUDA and OpenCL Implementations of 3D CT Reconstruction for Biomedical Imaging,
Saoni Mukherjee, Nicholas Moore, James Brock and Miriam Leeser.
Sixteenth IEEE High-Performance Extreme Computing Conference (HPEC). September 2012.
- OpenCL Floating Point Software on Heterogeneous Architectures - Portable or Not?,
Miriam Leeser, Jaideep Ramachandran, Thomas Wahl, and Devon Yablonski.
Fifth International Workshop on Numerical Software Verification (NSV).
July 2012.
- Cognitive Radio Universal Software Hardware,
George Eichinger, Kaushik Chowdhury, Miriam Leeser.
In Field Programmable Custom Computing Machines (FCCM).
April 2012.
- An FPGA Spectrum Sensing Accelerator for Cognitive Radio,
George Eichinger, Miriam Leeser and Kaushik Chowdhury.
In Fifteenth Annual Workshop on High-Performance Embedded Computing (HPEC2011).
September 2011.
- FPGA-based Acceleration of Hyperspectral K-Means Clustering,
David Kusinsky and Miriam Leeser.
In Fifteenth Annual Workshop on High-Performance Embedded Computing (HPEC2011).
September 2011.
- A Prototype FPGA for Subthreshold-Optimized CMOS,
Peter Grossmann and Miriam Leeser.
In Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2011).
February 2011.
- Sparse Matrix Algorithms on GPUs and their Integration into SCIRun, Devon Yablonski, Miriam Leeser and Dana Brooks. In
Fourteenth Annual Workshop on High-Performance Embedded Computing (HPEC2010). September 2010.
- Adaptable and Efficient Variable Size Template Matching in CUDA,
Nicholas Moore, Miriam Leeser and Laurie Smith King. In
Fourteenth Annual Workshop on High-Performance Embedded Computing (HPEC2010). September 2010.
- Adding support for GPUs to PVTOL: The Parallel Vector Tile Optimizing Library, James Brock, Miriam Leeser and Mark Niedre. In
Fourteenth Annual Workshop on High-Performance Embedded Computing (HPEC2010). September 2010.
- An FPGA Implementation of Incremental Clustering for Radar Pulse Deinterleaving, Scott Bailie and Miriam Leeser. In
Fourteenth Annual Workshop on High-Performance Embedded Computing (HPEC2010). September 2010.
- A Prototype FPGA Tile for Subthreshold-Optimized CMOS, Peter Grossmann and Miriam Leeser. In
Fourteenth Annual Workshop on High-Performance Embedded Computing (HPEC2010). September 2010.
-
Adapting the USRP as an Underwater Acoustic Modem,
Paul Ozog,
Miriam Leeser,
and Milica Stojanovic.
Thirteenth Annual Workshop on High-Performance Embedded Computing (HPEC2009).
September 2009.
-
Accelerating a MATLAB Application with Nvidia GPUs: a Case Study for GPU Library Construction,
Nicholas Moore and
Miriam Leeser.
Thirteenth Annual Workshop on High-Performance Embedded Computing (HPEC2009).
September 2009.
-
Accelerating Explicit State Model Checking on FPGAs: PHAST,
Mary Ellen Tie and
Miriam Leeser.
International Conference on Formal Methods and Models for Codesign (MEMOCODE).
July 2009.
-
Two-Dimensional Phase Unwrapping on FPGAs and GPUs,
Sherman Braganza and
Miriam Leeser.
Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA'08).
November 2008.
-
2D Phase Unwrapping on FPGAs and GPUs,
Sherman Braganza and
Miriam Leeser.
Twelfth Annual Workshop on High-Performance Embedded Computing (HPEC2008).
September 2008.
-
Extending VForce to Include Support for NVIDIA GPUs using CUDA,
Dennis Cuccaro,
Nicholas Moore,
Miriam Leeser,
and
Laurie Smith King.
Twelfth Annual Workshop on High-Performance Embedded Computing (HPEC2008).
September 2008.
-
Implementation of a Highly Parameterized Digital PIV System On Reconfigurable Hardware
,
Abderrahmane Bennis,
Miriam Leeser,
Gilead Tadmor, and Russ Tedrake.
Twelfth Annual Workshop on High-Performance Embedded Computing (HPEC2008).
September 2008.
- An Efficient Implementation Of A Phase Unwrapping Kernel On
Reconfigurable Hardware, Sherman Braganza and
Miriam Leeser.
IEEE International Conference on Application-specific Systems,
Architectures and Processors (ASAP 2008). July 2008.
- Phase Unwrapping On Reconfigurable Hardware, Sherman Braganza and
Miriam Leeser.
Eleventh Annual Workshop on High-Performance Embedded Computing
(HPEC2007). September 2007.
- FPGA Based Systolic Array Implementation of QR Transformation Using
Givens Rotations, Xiaojun Wang and
Miriam Leeser.
Eleventh Annual Workshop on High-Performance Embedded Computing
(HPEC2007). September 2007.
- Vforce: Aiding the Productivity and Portability in Reconfigurable
Supercomputer Applications via Runtime Hardware Binding, Nicholas Moore,
Miriam Leeser and
Laurie Smith King.
Eleventh Annual Workshop on High-Performance Embedded Computing
(HPEC2007). September 2007.
- The 1D Discrete Cosine Transform For Large Point Sizes Implemented On
Reconfigurable Hardware, Sherman Braganza and
Miriam Leeser.
IEEE International Conference on Application-specific Systems,
Architectures and Processors (ASAP 2007). July 2007.
- Performance Tuning on Reconfigurable Supercomputers: A Case Study,
Ben Cordes, Albert Conti,
Miriam Leeser, and
Eric Miller.
(Poster abstract), Supercomputing (SC'06). November 2006.
- Improving the Performance of Parallel Backprojection on a
Reconfigurable Supercomputer, Ben Cordes,
Miriam Leeser,
Eric Miller
and Richard Linderman. Tenth Annual Workshop on High-Performance Embedded
Computing (HPEC2006). September 2006.
- Heterogeneous Processing Element Support for VSIPL++,
Miriam Leeser,
Al Conti, Ben Cordes, Nicholas Moore, and
Laurie Smith King.
Tenth Annual Workshop on High Performance Embedded Computing (HPEC 2006).
MIT Lincoln Laboratory, Lexington, MA, September 19-20, 2006.
- VSIPL++ Support for Programming Reconfigurable Supercomputers.
Miriam Leeser,
Al Conti, Ben Cordes, Nicholas Moore and
Laurie Smith King.
Reconfigurable Systems Summer Institute (RSSI 2006) Conference,
co-sponsored by the National Center for Supercomputing Applications,
the Ohio Supercomputer Center, and the University of Manchester,
held at the University of Illinois Urbana-Champaign, Urbana, IL.
July 10-14, 2006.
- Acceleration of the 3D FDTD Algorithm in Fixed-point Arithmetic
using Reconfigurable Hardware, Wang Chen,
Miriam Leeser,
and Carey Rappaport. Progress in Electromagnetics Research Symposium
(PIERS 2006). March 2006.
- Efficient use of Communications Between an FPGA's Embedded Processor
and its Reconfigurable Logic, Joshua Noseworthy and
Miriam Leeser.
Fourteenth ACM International Symposium on Field-Programmable Gate Arrays
(FPGA2006). (Poster abstract). February 2006.
- An FPGA API for VSIPL++, Ben Cordes,
Miriam Leeser,
and Joe Tarkoff. Ninth Annual Workshop on High-Performance Embedded
Computing (HPEC2005), September 2005.
- Adapting Parallel Backprojection to an FPGA Enhanced Distributed
Computing Environment, Albert A. Conti, Ben Cordes,
Miriam Leeser,
Eric Miller
and Richard Linderman. Ninth Annual Workshop on High-Performance
Embedded Computing (HPEC2005). September 2005.
- Interface Techniques for Microprocessors Embedded Within FPGAs,
Joshua Noseworthy and
Miriam Leeser.
Ninth Annual Workshop on High-Performance Embedded Computing (HPEC2005).
September 2005.
-
Variable Precision Floating Point Division and Square Root,
Miriam Leeser
and Xiaojun Wang. Eighth Annual Workshop on High Performance Embedded
Computing (HPEC2004), pp. 47--48, September 2004.
-
Dynamo: A Runtime Codesign Environment, Heather Quinn,
Miriam Leeser and
Laurie Smith King.
Eighth Annual Workshop on High Performance Embedded Computing (HPEC2004),
pp. 65--66, September 2004.
-
Multimedia Macros for Portable Optimized Programs, Juan Carlos Rojas and
Miriam Leeser.
Seventh Annual Workshop on High Performance Embedded Computing (HPEC2003),
pp. 213--214, September 2003.
-
An FPGA Implementation of Two-Dimensional Finite-Difference Time-Domain
(FDTD) Algorithm, Wang Chen, Panos Kosmas,
Miriam Leeser and
Carey Rappaport.
Seventh Annual Workshop on High Performance Embedded Computing (HPEC2003),
pp. 105--106, September 2003.
-
Acceleration of the Retinal Vascular Tracing Algorithm Using FPGAs,
Shawn Miller and
Miriam Leeser.
Seventh Annual Workshop on High Performance Embedded Computing (HPEC2003),
pp. 133--134, September 2003.
-
Precision Modeling and Bit-Width Optimization of Floating-Point
Applications, Zhihong Zhao and
Miriam Leeser.
Seventh Annual Workshop on High Performance Embedded Computing (HPEC2003),
pp. 141--142, September 2003.
-
A Library of Parameterized Hardware Modules for Floating-Point Arithmetic
and Its Use, Pavle Belanovic and
Miriam Leeser.
Sixth Annual Workshop on High Performance Embedded Computing (HPEC2002),
pp. 45--46 September 2002.
-
Implementing Image Processing Pipelines in a Hardware / Software
Environment, Heather Quinn,
Miriam Leeser, and
Laurie Smith King.
Sixth Annual Workshop on High Performance Embedded Computing (HPEC2002),
pp. 29--31, September 2002.
- Parameterized K-means Clustering for Rapid Hardware Development to
Accelerate Analysis of Satellite Data,
Miriam Leeser,
Pavle Belanovic, Michael Estlick, Maya Gokhale, John Szymanski, and
James Theiler.
High Performance Embedded Computing (HPEC2001), November 2001.
- Employing Reconfigurable Hardware in a Networked Environment,
Miriam Leeser,
Heather Quinn, and
Laurie Smith King.
Fifth Annual Workshop on High Performance Embedded Computing
(HPEC2001), November 2001.
- Applying Reconfigurable Hardware to Segmentation for Multispectral
Imagery,
Miriam Leeser,
Michael Estlick, Natasha Kitaryeva, John Szymanski, and James Theiler.
-
High Performance Embedded Computing (HPEC2000), September 2000.