PhD for Benjamin Drozdenko

Title: Enabling Protocol Coexistence: Hardware-Software Codesign of Wireless Transceivers on Heterogeneous Computing Architectures

In an increasingly interconnected world, there has been an explosion in the number of wireless devices in the Internet of Things. This recent increase in wireless devices has been accompanied by a rising number of protocols for wireless communications, each focusing on different purposes such as execution time reduction, energy reduction, handling higher congestion levels, or operation at different bandwidths. This increase has also caused heavy congestion on particular bandwidths. Due to spectrum scarcity, the need has arisen for these devices to operate on the same bandwidths. However, existing wireless devices are inflexible and have no capabilities to coexist with devices using other protocols. Software-Defined Radios (SDR) have introduced new platforms for dynamically modifying wireless system designs, and heterogeneous computing has enabled implementation on different computing elements. Until now, researchers have focused on designing complete protocol-specific processing chains on static computing architectures. However, SDR has opened the door for flexibility in wireless transceivers, and heterogeneous computing systems can be used to meet the needs for lower execution time and power consumption.

This dissertation introduces new Field Programmable Gate Array (FPGA)-based design techniques to receive multiple protocols on the same computing platform. Our methods incorporate tunable parameters, such as FIR filter length and number of bits per fixed-point word, to explore design tradeoffs regarding clock cycle, resource utilization, power consumption, and detection accuracy. This research separates the physical (PHY) layer receive chains into a set of building blocks, including rate transition, pattern detection, and Orthogonal Frequency Division Multiplexing (OFDM) demodulation. This research introduces a practical resampling technique to accommodate several protocol rates while taking FPGA resource utilization into account. Having identified pattern detection as a time critical operation that needs to be performed with sufficient accuracy to avoid triggering false alarms, this research incorporates a hardware-friendly matched filtering technique to reduce FPGA utilization while maintaining detection accuracy. This research introduces a technique to use a single FFT to handle different numbers of frequency subcarriers. The implementation of the LTE physical downlink shared channel (PDSCH) and 802.11a protocols are implemented to test our techniques. LTE is the standard for high-speed wireless communication for mobile phones and data terminals; Wi-Fi uses variants of the IEEE 802.11a standard. To ease the system development process, this research develops models using MathWorks Simulink, which supports auto-generation of Hardware Description Language (HDL) code for the non-critical sections and incorporation of hand-tuned HDL code as part of its black box interface. These building blocks can be used by the wireless system modeling community to meet the needs of modern evolving wireless standards. This FPGA-based design framework for protocol coexistence is tested to support the receiver chains of 802.11a and LTE downlink protocols. FPGA-specific component designs are provided to support each protocol, including rate transition, matched filtering, and OFDM demodulation. This framework also provides a workflow for tuning parameter settings, such as filter length and fixed-point word size. In the future, this framework will allow researchers to achieve high-performance transceiver implementations on FPGA fabric for multiple cutting edge protocols.