PhD for Heather Quinn

Title:  Runtime Tools for Hardware/Software Systems with Reconfigurable Hardware

Abstract:

Hardware/software codesign tools help designers create efficient
systems that use hardware for speedup.  These tools include
co-specification, co-synthesis, and co-verification.  Co-synthesis
tools, the primary focus of this dissertation, translate a
co-specification into a hardware/software system.  This process
involves solving many intractable subproblems, such as partitioning a
design into hardware and software, synthesizing interfaces between
components, and allocating resources to hardware functions.

This dissertation focuses on hardware/software codesign tools for
Field Programmable Gate Arrays (FPGAs).  Reconfigurable
systems are inherently hardware/software systems, since the host
computer controls the reconfigurable device.  Reconfigurable devices
can exhibit speedups of up to three orders of magnitude over software;
however, overhead costs, such as hardware initialization,
communication, and reprogramming, must be kept to a small proportion
of the overall runtime.  Codesign tools for reconfigurable systems
help designers advantageously use FPGA technology provided they take
into account overhead as well as computation.

A set of tools were designed to support runtime codesign.  The
Software HArdware Runtime Procedural Partitioning (SHARPP) tool
applies linear optimization methods to solve a variation of the
hardware/software codesign partitioning problem for FPGAs called the
pipeline assignment problem.  The model for this optimization problem
takes into account the overhead costs associated with using FPGA
hardware and executing components serially.  These overhead costs,
which include communication and reprogramming, can be as much as 90\%
of a pipeline assignment's latency and are not accounted for in other
FPGA-based co-synthesis environments.  The Runtime Interfacing for
Pipeline Synthesis (RIPS) tool translates the SHARPP output into an
executable.  The Packet Exchange Platform (PEP) layer supports the
runtime execution of pipeline components through abstract interfaces.

These tools are applied to the image processing domain.  The tools
have access to a library called the image processing Basic Library of
Components (ipBLOC) that was developed as part of this research.  The
ipBLOC components are hardware and software implementations of common
image processing algorithms.  Java is used as a unifying platform for
both the hardware and software design processes.  The hardware
description is done in JHDL, a Java-based Hardware Description
Language for FPGAs.