MS for Haiqian Yu Title: Memory Architecture for Data Intensive Image Processing Algorithms in Reconfigurable Hardware Abstract: FPGA implementation is attractive for computationally intensive applications due to FPGA's speed and flexibility. Many of these applications, including image processing, are data-intensive at the same time. In most cases, off-chip memory banks have to be used to store the large amounts of data. Memory architecture organization then becomes critical for an optimized design since frequent memory accesses can result in long delays and degrade the system performance. A two-stage memory access structure, which utilizes locality of reference has proved to be a successful implementation. In this research, we apply this structure to the backprojection application. The idea of this expandable architecture can be generalized to apply to other data-intensive applications. An adaptive module is used in our implementation to isolate the core design and the memory interface. This extra module can greatly improve the re-use of the HDL code when migrating the design to a different hardware platform. Our implementation results show that the hardware system can work on different target FPGA computing boards with only a little modification. Moreover, performance is not affected on our current platform, we can achieve more than 100 times speedup over the software implementation.