MS Thesis Defense:  Jainik Kathiara 

Tuesday, January 4, 2011


Title : The Unified Floating Point Vector Co-processor (FPVC)

Abstract : There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option.

In this research we have implemented a high performance, autonomous floating point vector co-processor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC’s configuration and provide maximal performance.  The kernels implemented are from the area of linear algebra and include matrix multiplication and LU, QR and Cholesky decomposition.  We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.