MS Thesis for David Kusinsky

Title:

FPGA-based Hyperspectral Covariance Coprocessor for Size, Weight, and
Power Constrained Platforms  


ABSTRACT

Hyperspectral imaging (HSI) is a method of remote sensing that
collects many two-dimensional images of the same physical scene. Each
of these images corresponds to a single wavelength band in the
electromagnetic spectrum. The number of bands imaged by an HSI sensor
can be several hundred, and therefore a large amount of data is
produced. This data must be handled by the platform on which the HSI
sensor resides, either through onboard processing, or relaying
elsewhere. Hence, the platform plays an important role in defining the
capabilities of the entire remote sensing system. 

Size, weight, and power (SWaP) are important factors in the design of
any remote sensing platform. These remote sensing platforms, such as 
Unmanned Air Vehicles and microsatellites, are continually decreasing
in size.  This creates a need for remote sensing and image processing
hardware that consumes less area, weight, and power, while delivering
processing performance. The purpose of this research is to design and
characterize an FPGA-based hardware coprocessor that parallelizes the
calculation of covariance; a time-consuming step common in
hyperspectral image processing. The goal is to deploy such a board on
the remote sensing platform. 

The coprocessor is implemented using a Xilinx ML605 evaluation board.
The hardware used includes the Xilinx Virtex-6 FPGA, DDR3 memory, and
PCIe interface. An implementation to accelerate the covariance
calculation was created, and the OpenCPI open source framework was
adopted and modified to enable DDR3 memory and PCIe capabilities and
ease coprocessor testing. 

The coprocessor's performance is evaluated using several metrics:
total power (Watts), energy needed for processing (Joules), floating
point operations per Watt (FLOPS/W), and floating point operations per
Watt-kg (FLOPS/(W-kg)). Using these metrics, the design is compared to
a CPU-based processing platform and shown to have an overall SWaP
advantage. FLOPS/W and FLOPS/(W-kg) performance of the coprocessor is
2X and 2.75X that of the CPU-based platform, respectively. The
coprocessor requires 45% less energy than the CPU-based platform
during processing. 

This research shows that FPGA-based acceleration of HSI data
covariance computations is promising from a size, weight, and power
perspective. Significant unused FPGA resources in the coprocessor's
FPGA can be used to add additional HSI data processing operations and
direct HSI camera interfacing in the future. 

[This work is sponsored by the Department of the Air Force under Air
Force Contract #FA8721-05-C-0002.  Opinions, interpretations,
conclusions and recommendations are those of the author and are not
necessarily endorsed by the United States Government.  Approved for
public release; distribution is unlimited.]