MS Thesis Defense for Joshua Noseworthy

Title:  Enabling Communications Between an FPGA’s Embedded 
Processor and its Reconfigurable Resources

Abstract:

Increasing device densities allow designers to integrate more 
functionality onto a single piece of silicon. Many chip manufacturers 
are using this flexibility to offer complete solutions that can 
be integrated onto a single device. FPGA manufacturers, such 
as Xilinx and Altera, have introduced FPGA architectures that 
contain a variety of embedded processing elements along with 
the device's reconfigurable logic. One of the more recent processing 
elements that has been introduced by Xilinx is the PowerPC405 
hard-core processor.

One of the challenging aspects of developing applications that 
target the PowerPC is the interfacing of the processor with the 
surrounding reconfigurable logic. We have implemented several 
versions of a FM3TR Waveform Application to exercise the various 
interfaces that enable communication between the processor and 
the surrounding FPGA fabric. These interfaces can be either shared 
or dedicated. Shared interfaces enable communication between the 
processor and multiple peripherals. Dedicated interfaces provide 
dedicated communication links between the processor and a single 
peripheral. Dedicated interfaces are less flexible, but can deliver 
higher performance than shared interfaces. Our results indicate 
that the performance of the FM3TR Waveform Application can be 
increased by as much as 60% just by choosing the interfaces that 
are most appropriate for the implementation. This demonstrates 
that the performance of FPGA applications that use the embedded 
processor are dramatically effected by the mechanisms that are 
chosen to enable communication between the processor and its 
surrounding resources.