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PhD Defense: Inseok Jung

31
Jul

442 Dana

July 31, 2014 11:00 am to 12:00 pm
July 31, 2014 11:00 am to 12:00 pm

July 31, 2014

11:00-12:00

442 Dana Research Center

 

Title : Self-Calibration Approach for Mixed Signal Circuits in Systems-on-Chip

 

Abstract : 

MOSFET scaling has served industry very well for a few decades by proving improvements in transistor performance, power, and cost. However, they require high test complexity and cost due to several issues such as limited pin count and integration of analog and digital mixed circuits. Therefore, self-calibration is an excellent and promising method to improve yield and to reduce manufacturing cost by simplifying the test complexity,  because it is possible to address the process variation effects by means of self-calibration technique. Since the prior published calibration techniques were developed for a specific targeted application, it is nit easy to be utilized for other applications. In order to solve the aforementioned issues, in this dissertation, several novel self-calibration design techniques in mixed-signal mode circuits are proposed for an analog to digital converter (ADC) to reduce mismatch error and improve performance. These are essential components in SOCs and the proposed self-calibration approach also compensates the process variations. The proposed novel self-calibration approach targets the successive approximation (SA) ADC. First of all, the offset error of the comparator in the SA-ADC is reduced using the proposed approach by enabling the capacitor array in the input nodes for better matching. In addition, the auxiliary capacitors for eachcapacitor of DAC in the SA-ADC are controlled by using synthesized digital controller to minimize the mismatch error of the DAC. Since the proposed technique is applied during foreground operation, the power overhead in SA-ADC case is minimal because the calibration circuit is deactivated during normal operation time. Another benefit of the proposed technique is that the offset voltage of the comparator is continuously adjusted for every step to decide one-bit code, because not only the inherit offset voltage of the comparator but also the mismatch of DAC are compensated simultaneously. Synthesized digital calibration control circuit operates as fore-ground mode, and the controller has been highly optimized for low power and better performance with simplified structure.   In addition, in order to increase the sampling clock frequency of proposed self-calibration approach, novel  variable clock period method is proposed. 

To achieve high speed SAR operation, a variable clock time technique is used to reduce not only peak current but also die area. The technique removes conversion time waste and extends the SAR operation speed easily. To verify and demonstrate the proposed techniques, a prototype charge-redistribution SA-ADCs with the proposed self-calibration is implemented in 130nm standard CMOS process. The prototype circuit's silicon area is 0.0715 mm^2 and consumers 4.62mW with 1.2V power supply.

 

Thesis Committee:

Prof. Fabrizio Lombardi

Prof. Marvin Onabajo

Prof. Yong-Bin Kim (advisor)