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PhD Defense: Jiaxing Zhang

11
Aug

442 Dana

August 11, 2014 9:00 am to 11:00 am
August 11, 2014 9:00 am to 11:00 am

Name: Jiaxing Zhang

Title: Integrating Algorithm-Level Design and System-Level Design through Specification Synthesis

Date: Monday, August 11th, 9am-11am

Location: 442 Dana

Abstract:
Modern Multiprocessor System-On-Chip (MPSoC) designs face challenges in tremendous design complexity imposed by the wide range of functional requirements and versatile architectural platforms. The Electronic Design Automation (EDA) research has been striving to accelerate the creation, deployment and validation cycles from initial design modeling to final system delivery. However, establishing a universal, automatic and rapid design flow from concept modeling to heterogeneous implementations with synthesis, optimization and exploration capability remains an open challenge due to the overwhelming complexity, vastly different abstractions, and market adaptability and usability.

In this thesis, we introduced a specification synthesis approach that conjoins two mature and active design methodologies, Algorithm-Level Design (ALD) and System-Level Design (SLD), to establish a new Algorithm-Architecture Co-design flow. We designed and implemented an algorithm-to-specification synthesizer: Algo2Spec, which out of an algorithm model captured in ALD, such as Simulink, synthesizes into an SLD languages (SLDL) specification (e.g. SpecC/SystemC) enabling SLD exploration. Expanding the rich sets of SLD facilities into higher abstraction levels in ALD forms a new joint co-design methodology. The new flow seamlessly spans from the Simulink environment down to heterogeneous implementations crossing multiple abstractions. Our tools empower designers to construct, simulate, validate, explore, and deploy models in rapid feedback cycles. Our results illustrated the opportunities and benefits of our approach on a set of real-world applications and showed significantly shortened design time.

In addition, we explored new optimization opportunities emerged from the specification synthesis with respect to Design Space Exploration (DSE) and software synthesis. We have identified several DSE challenges, such as selecting a suitable model granularity to balance the model mapping flexibility, specification quality as well as synthesis constraints (i.e. computation/communication efficiency and scheduling). We designed an array of multi-objective heuristics to address these challenges to reduce the DSE complexity and overhead while simultaneously increase the specification performance. Moreover, once certain DSE constraints are relaxed, such as model-to-platform being provided, we ensure the generated specification with maximized computation efficiency and reduced communication overhead. As both ALD and SLD incorporate the principles of the component-based design, a certain degree of modeling flexibility, gained by using abstracted component compositions, appears in both domains. However, such beneficial flexibility becomes overhead once the model, passing high-level modeling and exploration periods, enters the back-end synthesis phase. In software synthesis, such flexibility comes at a cost of run-time call site resolution. We investigated into the impeded performance in current embedded software synthesis from SLDL specifications. The results expressed that by eliminating unnecessary flexibility overhead such as dynamic dispatch, the SLDL-to-C compiler achieved better performance on embedded processors, improved readability, and debuggability compare to current solutions.

The outcome of the work greatly simplifies the Algorithm-Architecture Co-design with new tools, methodologies, and optimizations. The thesis has demonstrated how the new design flow and methods can deeply enhance current algorithm design solutions to leverage the vastly available computing power in today’s heterogeneous architectures.

Committee:
Prof. Gunar Schirner (Advisor)
Prof. Miriam Leeser
Prof. David Kaeli