|The newest VFLOAT library can be downloaded here.||December, 2014|
Previous update: Major revision of VFLOAT available December 2013.
We have developed a library of fully parameterized hardware modules for variable precision floating-point arithmetic. The library includes modules for format control, arithmetic operators and conversion to and from any fixed-point format. All the modules have been implemented in VHDL and designed to run on different FPGA devices, including Xilinx and Altera FPGAs.
An important feature of these modules is that denormalize, and normalize/round are decoupled from the arithmetic operations. This gives the designer full control over where and when to normalize floating point calculations, and results in savings of area in their hardware implementation. The currently implemented arithmetic operators are floating point add/sub, multiply, reciprocal, divide, square root, accumulate and multiply accumulate.
Please let us know if you are using the library by sending email to Prof. Miriam Leeser. We would also like to receive bug reports. We will do our best to keep the library up to date.
Click here for a graph of the dependences for each of the modules in the library.
VFLOAT can be downloaded here. Library Revision from December 2014.
It is required that library users instantiate your own multipliers (mul, recip, div, sqrt) and lookup tables (recip, div and sqrt). Read the readme.txt file for details.
To use these modules, first unzip the zip file in directory fp_lib and then compile all the vhd files required for any operator or format controller. The dependencies of these modules can be found by clicking on the hyperlink on the left side of the dependency graph .
Below are some examples that implement basic single precision IEEE operations such as addition and multiplication.
|Example name||Download link|
|IEEE square root||Square root|
Accumulator and Multiply-Accumulate are provided: The Multiply-Accumulate is based on an adder tree and the Accumulator is created using a single adder and feedback path. Clock latency for Multiply-Accumulate is fixed and it is variable for Accumulator.
|Archive details||Date||Download link|
|Major Version Update||Dec, 2013||Here|
|Updated version of divider from 2008||Sep, 2010||Here|
|Library with old divider and square root operator||Feb, 2008||Here|
|New accumulator||Nov, 2007||Here|
|Fixed float2fix and fix2float||Oct, 2005||Here|
|Original library||June, 2002||Here|
If you have any questions or problems using the library, please contact Miriam Leeser
Xin Fang and Miriam Leeser. "Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs, IEEE High Performance Extreme Computing (HPEC), September 2013, Waltham, MA.
X. Wang and M. Leeser, VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware, ACM Transactions on Reconfigurable Technology and Systems. Vol. 3 No. 3, September 2010.
X. Wang and M. Leeser, A Truly Two Dimensional Systolic Array FPGA Implementation of QR Decomposition, ACM Transactions on Embedded Computer Systems. Vol. 9 No. 1, October 2009.
X. Wang, M. Leeser, and S. Braganza, Advanced Components in the Variable Precision Floating-Point Library, Field-programmable Custom Computing Machines (FCCM) 2006, April 2006, Napa CA.
X. Wang, M. Leeser, and H. Yu, A Parameterized Floating-Point Library Applied to Multispectral Image Clustering, 7th Annual MAPLD International Conference, September 2004, Washington DC.
X. Wang and M. Leeser,Variable Precision Floating Point Division and Square Root,8th Annual High Performance Embedded Computing Workshop,October 2004, Lexington, MA.
Pavle Belanovic and Miriam Leeser, A Library of Parameterized Floating Point Modules and Their Use.12th International Conference on Field Programmable Logic and Application. September 2002.
Pavle Belanovic Library of Parameterized Hardware Modules for Floating-Point Arithmetic with An Example Application M.S. Thesis, Dept of Electrical and Computer Engineering, Northeastern University, June 2002
Faculty: Dr. Miriam Leeser
Graduate Students: Xin Fang, Pavle Belanovic, Haiqian Yu, Sherman Braganza, Xiaojun Wang, Jainik Kathiara
Lab Visitors: Paolo Palana.
Reconfigurable Computing Lab
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.